1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device in which a plurality of memory cells are arrayed in specific fashion, and a method for performing a verify write operation on that device.
2. Description of the Related Art
There exist methods (such as one disclosed in Japanese Patent Laid-open No. 2007-242191; called Patent Document 1 hereunder) for raising the number of bits to be programmed simultaneously in order to increase the speed at which to write illustratively to NOR type nonvolatile semiconductor memory (flash memory) devices. The methods of this kind are aimed at achieving enhanced write speeds by simultaneously verify-read numerous bits in a program verify read operation.
Such techniques for faster programming are not limited to the existing nonvolatile memory devices; they may also be applied extensively to other types of nonvolatile memory devices including resistance-variable type memory devices disclosed in Japanese Patent Laid-open No. 2005-235360 (called Patent Document 2 hereunder).
Illustratively for NOR type flash memories, the write speed is typically about 100 μsec. per bit and the write current is about 100 μA as discussed in Patent Document 1 as part of the related art. When data is written 8 to 32 bits at a time upon programming, a program throughput of 8 to 32 bits/10 μsec. (=100 kilobytes/sec. to 400 kilobytes/sec.) is attained. The write current necessary for the operation is approximately 800 μA to 3.2 mA.
The above-cited Patent Document 1 proposes arrangements for securing the current paths on which a voltage drop over wiring is limited when a large current is supplied to deal with growing numbers of bits to be programmed simultaneously. These arrangements are designed to boost program throughput.